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Operating Modes
• The
TDV01
logic. This signal is active only during transmit channels.
• The transfer is received on channel 0 (word 0), and transmits on
channels 1 and 2 (word 1 and 2)
SPORT1_CLK
SPORT1_DA/B
SPORT1_FS
SPORT0_DA/B
TDV01
Figure 6-7. Multichannel Operation
Multichannel Mode Control Bits
Several bits in the
nel mode operation:
• Operation mode (
• Master mode (
• Sampling edge frame sync/data (
• Internal frame sync (
• Logic level frame sync (
• Word length (
• Channel enable (
6-44
www.BDTIC.com/ADI
(
) is used as transmit data valid for external
SPORT0_FS
WORD 0
B0
B2
B2
B1
control register enable and configure multichan-
SPCTLx
) = 0 (disable non-multichannel)
OPMODE
ICLK)
)
IMFS
/
LMFS
LTDV
) (3–32 bits)
SLEN
or
SPEN_A
SPEN_B
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
WORD 1
IGNORED
B3
B2
B1
B0
)
CKRE
)
)
WORD 2
B3
B2
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