Table of Contents
Advertisement
Ratio Registesr (SRCRATx)
The
and
SRCRAT0
to input sampling frequency. This ratio is reported in 4.11 (integer.frac-
tion) format where the 15-bit value of the normal binary number is
comprised of 4 bits for the integerand 11 bits for the fraction. The
register indicates the sample rate ratio of
The
SRCx_MUTEOUT
signal. Once the
MUTE_OUT
can be read.
All
SRCx_MUTEOUT
Operation Modes
The SRC can operate in TDM, I
phase (ADSP-21364 only), and bypass modes. The serial ports of the pro-
cessor can be used for moving the SRC data to/from the internal memory.
2
In I
S, left-justified and right-justified modes, the SRCs operate individu-
ally. The serial data provided in the input port is converted to the sample
rate of the output port.
formats.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Asynchronous Sample Rate Converter
registers can be read to find the ratio of output
SRCRAT1
bits in
register report the status of the
SRCRATx
SRCx_MUTEOUT
bits in
SRCRATx
2
S, left-justified, right-justified, matched
Figure 12-3
shows the timing in the various
÷
SRCx_FS_OP_I
SRCx_FS_IP_I
signal is cleared then the ratio
register are set after reset.
SRCRAT
.
12-13
Advertisement
Table of Contents
