Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 398

Functional Description
Automatic Mute
The mute feature of the SRC can be controlled automatically in hardware
using the
MUTE_IN
that by default, the
signal, but not vice versa. Automatic muting can be disabled by
MUTE_OUT
setting (=1) the
Soft Mute
When the
SRCx_SOFTMUTE
nal is asserted, and the SRC performs a soft mute by linearly decreasing
the input data to the SRC FIFO to zero, (–144 dB) attenuation as
described for automatic hardware muting.
A 12-bit counter, clocked by
attenuation. Therefore, the time it takes from the assertion of
–144 dB, full mute attenuation is 4096 FS cycles.
Likewise, the time it takes to reach 0 dB mute attenuation from the
de-assertion of
Hard Mute
When the
SRCx_HARD_MUTE
diately mutes the input data to the SRC FIFO to zero, (–144 dB)
attenuation.
Auto Mute
When the
SRCx_AUTO_MUTE
municates with the S/PDIF receiver peripheral to determine when the
input should mute. Each SRC is connected to the S/PDIF receiver to read
the
DIR_NOAUDIO
page A-75). When the
mutes the input data to the SRC FIFO to zero, (–144 dB) attenuation.
12-10
www.BDTIC.com/ADI
signal by connecting it to the
register connects the
SRCMUTE
bits in the
SRCx_MUTE_EN
bit in the
SRCx_FS_IP_I
is 4096 FS cycles.
MUTE_IN
bit in the
bit in the
bits (see"Receive Status Register (DIRSTAT)" on
DIR_NOAUDIO
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
MUTE_OUT
MUTE_IN
register.
SRCMUTE
register is set, the
SRCCTL
, is used to control the mute
register is set, the SRC imme-
SRCCTL
register is set, the SRC com-
SRCCTLx
bit is set (=1), the SRC immediately
signal. Note
signal to the
sig-
MUTE_IN
to
MUTE_IN