Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 490

Power Management Control Register (PMCTL)
Table A-1. SYSCTL Register (Cont'd)
Bit Name
27 PWM1EN
28 PWM2EN
29 PWM3EN
31–30 Reserved
Power Management Control
Register (PMCTL)
The following sections describe the regi s ters associated with the processors
power management functions.
The power management control register, shown in
memory-mapped register. This register contains bits to control phase lock
loop (PLL) multiplier and divider (both input and output) values, PLL
bypass mode, and clock enabling control for peripherals (see
page A-8). This register also contains status bits, which keep track of the
status of the
CLK_CFG
dent on the
CLK_CFG
The core can write to all bits except the read-only status bits. The
bit is a logical bit, that is, it can be set, but on reads it always responds
with zero.
A-6
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Description
Pulse Width Modulation1 Mode Select.
0 = AD15–12 pins in parallel port mode
1 = AD15–12 pins in PWM mode
Pulse Width Modulation2 Mode Select.
0 = AD3–0 pins in parallel port mode
1 = AD3–0 pins in PWM mode
Pulse Width Modulation3 Mode Select.
0 = AD7–4 pins in parallel port mode
1 = AD7–4 pins in PWM mode
pins (read-only). The reset value of
pins (bits 5–0).
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
Figure A-2, is a 32-bit
Table A-2 on
is depen-
PMCTL
DIVEN