Table of Contents
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Index
parallel port
pins, 4-3,
4-9
polarity,
4-5
read cycle,
4-5
registers, 4-10,
A-10
restrictions in use,
4-13
signals,
4-3
SRAM memory,
4-8
stalls in,
4-17
system
configure and enable,
TCB,
2-30
throughput, 4-19, 4-21,
transfer protocol,
4-8
write cycle,
4-5
parallel port bits
ALE polarity level (PPALEPL),
buffer hang disable (PPBHD),
bus hold cycle enable (PPBHC), 4-8,
4-17,
A-12
bus status (PPBS), 4-16,
data cycle duration (PPDUR), 4-8,
DMA enable (PPDEN),
DMA status (PPDS) bit,
enable (PPEN),
A-12
external data width (PP16),
FIFO status (PPS),
A-13
hold cycle (PPBHC),
parallel port chaining status (PPCHS),
A-14
PP16 (external data width),
PPBHD (buffer hang disable),
PPBS (bus status),
A-13
PPDEN (DMA enable),
PPDS (parallel port DMA status),
PPEN (enable),
A-12
PPI (parallel port interrupt), 4-16,
PPS (FIFO status),
A-13
PPTRAN (transmit/receive select),
I-14
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(continued)
A-11
A-12
A-13
A-13
A-13
A-12
A-12
A-13
A-12
4-8
A-12
A-13
A-12
A-13
4-18
A-12
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
parallel port bits
transmit/receive select (PPTRAN), 4-6,
4-24,
4-25
PCG
active low frame sync select for frame
sync (INVFSx) bits,
bypass mode,
13-13
clock A source (CLKASOURCE) bit,
A-67
clock input (CLKIN) pin, 13-3,
control (PCG_CTL_Ax) registers,
13-15,
A-66
division ratios,
13-17
frame sync A source (FSASOURCE) bit,
13-15,
A-67
frame sync B source (FSBSOURCE) bit,
13-15
frame syncs,
13-13
frequency of the frame sync output,
13-10
one shot frame sync A or B (STROBEx)
bits,
13-13
one shot option,
13-14
PCG_CTLA0 (control) register,
phase shift of frame sync,
pulse width (PCG_PW) register, 13-13,
13-14
2
setup for I
S or left-justified DAI
example,
13-16
synchronization with the external clock,
13-9
PCI (program control interrupt) bit, 2-22,
2-23, 2-27, 2-28,
4-13
parallel port, 4-14,
4-19
SPI,
7-12
SPORTs,
6-52
PCM audio,
11-18
PDAP
enable (IDP_PDAP_EN) bit,
(continued)
13-13
13-21
A-66
13-11
A-52
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