Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 529

Table A-18. SPMCTLxy Register Bit Descriptions (Cont'd)
Bit Name
22–16 CHNL
23 MCEB
27–24 DMASxy
31–28 DMACHSxy
SPORT Transmit Select Registers (MTxCSy)
Each bit, 31–0, set (= 1) in one of four
active transmit channel, 127–0, on a multichannel mode serial port.
When the
MTxCSy
word in that channel's position of the data stream. When a channel's bit
in the register is cleared (= 0), the serial port's data transmit pin
MTxCSy
three-states during the channel's transmit time slot.
SPORT Transmit Compand Registers (MTxCCSy)
Each bit, 31–0, set (= 1) in one of four
companded transmit channel, 127–0, on a multichannel mode serial port.
When the
MTCCSx
port applies the companding from the
word in that channel's position of the data stream. When a channel's bit
ADSP-2136x SHARC Processor Hardware Reference
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for the ADSP-21362/3/4/5/6 Processors
Description
Current Channel Selected. Identifies the currently selected transmit
channel slot (0 to 127).
(Read-only, sticky)
Multichannel Enable, B Channels.
0 = Disable
1 = Enable
DMA Status. Defines the DMA A/B channel status for the SPORTs
x=0, 2, 4 and y=1, 3, 5
0 = DMA Inactive
1 = DMA Active
(Read-only)
DMA Chaining Status. Defines the DMA Chaining A/B channel sta-
tus for the SPORTs x=0, 2, 4 and y=1, 3, 5
0 = DMA Chain Loading inactive
1 = DMA Chain Loading active
(Read-only)
registers activate a channel, the serial port transmits the
register activates companding for a channel, the serial
Registers Reference
registers corresponds to an
MTxCSy
registers corresponds to a
MTxCCSx
selection to the transmitted
DTYPE
A-45