Table of Contents
Advertisement
/* Fill the source buffer */
lcntr=LENGTH(source), do fill until lce;
dm(i0,1)=r0;
fill: r0=rot r0 by 1;
/* Set the interrupt mask for MTMDMA */
bit set imask MTMI;
bit set mode1 IRPTEN;
/* Flush the MTMDMA FIFO */
r0=MTMFLUSH;
dm(MTMCTL)=r0;
/* Set up the source address to read */
r0=source;
dm(IIMTMR)=r0;
/* Set up the destination address to write */
r0=dest;
dm(IIMTMW)=r0;
/* Read and write sequentially with a step of 1 */
r0=1;
dm(IMMTMW)=r0;
dm(IMMTMR)=r0;
/* Read the number of words in source */
r0=length(source);
dm(CMTMR)=r0;
/* Write the number of words in destination */
r0=length(dest);
dm(CMTMW)=r0;
/* Enable MTMDMA */
r0=MTMEN;
dm(MTMCTL)=r0;
_main.end: jump(pc,0);
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Memory-to-Memory Port DMA
3-5
Advertisement
Table of Contents
