Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 169

the shaded cells denote that the bits have same function in all operating
modes.
Table 6-4. SPCTLx Control Bit Comparison
Bit Standard Serial Mode
0 SPEN_A
1 DT YPE
2 DT YPE
3 LSB F
4 SLEN0
5 SLEN1
6 SLEN2
7 SLEN3
8 SLEN4
9 PACK
10 ICL K
11 OPMODE
12 CKRE
13 FS R
14 IFS
15 DIFS
16 LFS
17 LAF S
18 SDEN_A
19 SCHEN_A
20 SDEN_B
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
2
I S and Left-Justified
Transmit Control Bits
Mode
(SPORT0, 2, 4)
SPEN_A Reserved
Reserved DTYPE
Reserved DTYPE
Reserved LSBF
SLEN0 SLEN0
SLEN1 SLEN1
SLEN2 SLEN2
SLEN3 SLEN3
SLEN4 SLEN4
PACK PACK
MSTR Reserved
OPMODE OPMODE
Reserved CKRE
Reserved Reserved
Reserved Reserved
DIFS Reserved
L_FIRST LTDV
LAFS Reserved
SDEN_A SDEN_A
SCHEN_A SCHEN_A
SDEN_B SDEN_B
Serial Ports
Multichannel Mode
Receive Control
Bits (SPORT1, 3, 5)
Reserved
DTYPE
DTYPE
LSBF
SLEN0
SLEN1
SLEN2
SLEN3
SLEN4
PACK
ICLK
OPMODE
CKRE
Reserved
IMFS
Reserved
LMFS
Reserved
SDEN_A
SCHEN_A
SDEN_B
6-11