Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 321

Maximum period = 2 × (2

If your application requires a more sophisticated PWM output
generator, refer to
Single-Pulse Generation
If the bit is cleared, the
PRDCNT
the signal. This mode can also be used to implement a well
TIMERx_O
defined software delay that is often required by state machines. The pulse
width (= 2 x
TMxW
should be set to a value greater than the pulse width register.
At the end of the pulse, the interrupt latch bit (
timer is stopped automatically. If the
is generated on the
active low.
Pulse Mode
The waveform produced in PWM_OUT mode with
has a fixed assertion time and a programmable deassertion time (via the
register). When three timers are running synchronously by the same
TMxW
period settings, the pulses are aligned to the asserting edge as shown in
Figure 9-4.
Note that the timer does not support toggling of the
period.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
31
– 1) × 7.5 ns = 32 seconds.
Chapter 10, Pulse Width
PWM_OUT
) is defined by the width register and the period register
signal. If the
TIMERx_O
Peripheral Timers
Modulation.
mode generates a single pulse on
) is set and the
TIMxIRQ
bit is set, an active high pulse
PULSE
bit is not set, the pulse is
PULSE
PRDCNT
PULSE
= 1 normally
bit in each
9-13