Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 524

Peripherals Routed Through the DAI
Table A-17. SPCTLx Register Bit Descriptions (Multichannel)
Bit Name
0 Reserved
2–1 DTYPE
3 LSBF
8–4 SLEN
9 PACK
10 ICLK
11 OPMODE
12 CKRE
13 Reserved
A-40
www.BDTIC.com/ADI
Description
Data Type Select. Selects the data type formatting for standard serial
mode transmissions. For Standard serial mode, selection of companding
mode and MSB format are exclusive:
Multichannel Data Type Formatting
00 Right-justify, zero-fill unused MSBs
01 Right-justify, sign-extend unused MSBs
10 Compand using
11 Compand using A-law
The transmit shift register does not zero-fill or sign-extend transmit
data words; this only takes place for the receive shift register.
Serial Word Endian Select.
0 = Big endian (MSB first)
1 = Little endian (LSB first)
Serial Word Length Select. Selects the word length in bits. Word sizes
can be from 3 bits (SLEN = 2) to 32 bits (SLEN = 31).
16-bit to 32-bit Word Packing Enable.
0 = Disable 16- to 32-bit word packing
1 = Enable 16- to 32-bit word packing
Internal Clock Select. Select the receiver clock for SPORT(1/3/5)
0 = Select external receiver clock
1 = Select internal receiver clock
Note: For the transmitter clock (SPORT0/2/4) bit is reserved
Sport Operation Mode.
0 = multichannel mode
Note for multichannel operation, the SPMCTLxy registers must be
programmed
Clock Rising Edge Select. Determines clock signal to sample data and
the frame sync selection.
0 = Falling edge
1 = Rising edge
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
μ
-law