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Unlike previous SHARCs, the 8 to 48-bit packing mode for
instructions is not supported. For instructions, the DMA reads
3 x 32-bit data which results in 2 x 48-bit instructions.
Also unlike previous SHARC processors, the ADSP-21362/3/4/5/6
processors do not have a boot memory select (
FLASH/EPROM's chip select (
address decoder, or otherwise derived from the parallel port signals.
For more information, see Chapter 4, Parallel Port.
The parallel port bits used in booting are shown in
complete description of the parallel port control register, see
Control Register (PPCTL)" on page
of this register has changed to 0x0000402E in no boot mode (reserved).
Table 14-10. PPCTL Boot Settings (0x412F)
Bit
PPEN (bit 0)
PPDUR (bits 5–1)
PPBHC (bit 6)
PP16 (bit 7)
PPDEN (bit 8)
PPTRAN (bit 9)
PPBHD (bit 12)
PPALEPL (bit 13)
PPFLMD (bit 14)
The parallel port DMA channel is usedwhen downloading the boot kernel
information to the processor. At reset, the DMA parameter registers are
initialized to the values listed in
In this configuration, the loader kernel is read via DMA from the FLASH.
If the application needs to speed-up read accesses, programs should
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
CS
A-11. Note that after reset, the value
Setting
= 1; enable parallel port
= 10111; (23 core clock cycles per data transfer cycle)
= 0; do not insert a bus hold cycle on every access
= 0; external data width = 8 bits
= 1; use DMA
= 0; receive (read) DMA
= 0; buffer hang enabled
= 0; ALE is active high
= 1; enable flash mode
Table
14-11.
System Design
) pin. The boot
BMS
) should be generated from an
Table
14-10. For a
"Parallel Port
14-37
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