Registers - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

Table of Contents

Registers

application program must use the correct serial port data buffers, accord-

ing to the value of

data buffers for the transmission of A and B channel data, or it enables the

receive data buffers for the reception of A and B channel data. Inactive

data buffers are not used.

When programming the serial port channel (A or B) as a transmitter, only

the corresponding transmit buffers

while the receive buffers (

when SPORT channels A and B are programmed to receive, only the cor-

The processor's SPORTs are not UARTs and cannot communicate with

an RS-232 device or any other asynchronous communications protocol.

One way to implement RS-232 compatible communication with the pro-

cessor is to use two of the

transmit signals.

The ADSP-2136x processor has six seri a l ports. Each SPORT has two data

paths corresponding to channel A and channel B.

The registers used to control and configure the serial ports are part of the

IOP register set. Each SPORT has its own set of 32-bit control registers

and data buffers.

The main control register for each serial port is the serial port control reg-

. These registers are described in

When changing operating modes, clear the serial port control regis-

ter before the new mode is written to the register.

registers control the operatingmodes of the serial ports for the

I/O processor.

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buffers are activated.

pins as asynchronous data receive and

lists all the bits in the

ADSP-2136x SHARC Processor Hardware Reference

for the ADSP-21362/3/4/5/6 Processors

bit enables either the transmit

become active,

) remain inactive. Similarly,

"Serial Port Registers" on