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The
pin is active high by default, but can be set active low via the
ALE
bit (bit 13) in the parallel port control (
PPALEPL
Since
ALE
port boot mode must use address latching hardware that can pro-
cess this active high signal. For complete information on using the
parallel port for booting, see
page
14-36.
Data Cycles
In a read cycle, the
strobed. If the upper 16 bits of the external address have changed, this
cycle is always preceded by an
the address,
A7–0
the
pins with the rising edge of
AD7–0
not driven in the read cycle, the external address is provided entirely by
the external latch, and data is latched from the
edge of
. Read cycles can be lengthened by configuring the parallel port
RD
data cycle duration bits in the
In a write cycle, the
strobed. If the upper 16 bits of the external address have changed, this
cycle is always preceded by an
the address are driven on the
pins. In 16-bit mode, address bits are not driven in the write cycle. The
external address is provided entirely by the external latch, 16-bit data is
driven onto the
with the rising edge of the
the falling edge of
setup and hold time with respect to the
lengthened by configuring the parallel port data cycle duration bits in the
register.
PPCTL
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
polarity is active high by default, systems using parallel
and
signals are inactive and the
WR
ALE
cycle. In 8-bit mode, the lower 8 bits of
ALE
, are driven on the
PPCTL
and
signals are inactive and the
RD
ALE
cycle. In 8-bit mode, the lower 8 bits of
ALE
AD15–8
pins, and data is written to the external device
AD15-0
signal. Address and data are driven before
WR
and deasserted after the rising edge to ensure enough
WR
) register.
PPCTL
"Parallel Port Booting" on
pins, and data is latched from
AD15–8
. In 16-bit mode, address bits are
RD
pins with the rising
AD15–0
register.
pins and data is driven on the
signal. Write cycles can be
WR
Parallel Port
signal is
RD
signal is
WR
AD7–0
4-5
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