Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 291

PDAP_ CLK_ I
PDAP_ HO LD_ I
P DAP DATA
P DAP_ STROBE_ O
PDAP _CLK_I
P DAP _HOLD_I
PDAP DATA
PDAP_S TRO BE _O
Figure 8-11. PDAP Hold Input (Mode = 00, Pack by 4))
As shown in the figures,
tive edges of the clock (falling edge in the above figures) and these signals
are sampled by the active edge of the clock (rising edge in the figures).
Data Buffer
The register (shown in
IDP_FIFO
(IDP_FIFO)" on page
the 8-deep IDP FIFO which have been filled by the SIP or the PDAP
units. Normally, this register is used only to read and remove the top sam-
ple from the FIFO. Channel encoding provides for eight serial input types
that correspond to the
using channels 0–7 in serial mode, this register format applies. When
using channel 0 in parallel mode, refer to the description of the packing
bits for PDAP mode.

The information in
the PDAP channel.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
B0 B1 B2
B0 B1
and
PDAP_DATA
"Input Data Port FIFO Register
A-53) provides information about the output of
bits in the IDP control registers. When
IDP_SMODEx
Table A-22 is not valid when data comes from
Input Data Port
B0
B3
B2
B3
are driven by the inac-
PDAP_HOLD
8-17