Table of Contents
Advertisement
Master boot mode is used when the processor is booting from an
SPI-compatible serial PROM, serial FLASH, or slave host processor. The
specifics of booting from these devices are discussed individually. On
reset, the interface starts up in master mode performing a 384 32-bit word
DMA transfer.
SPI master booting uses the default bit settings shown in
Table 14-12. SPICTL Master Boot Settings (0x5D06)
Bit
Setting
SPIEN
Set (= 1)
SPIMS
Set (= 1)
MSBF
Cleared (= 0)
WL
10
DMISO
Cleared (= 0)
SENDZ
Set (= 1)
SPIRCV
Set (= 1)
CLKPL
Set (= 1)
CPHASE
Set (= 1)
The SPI DMA channel is used when downloading the boot kernel infor-
mation to the processor. At reset, the DMA parameter registers are
initialized to the values listed in
Table 14-13. Parameter Initialization Values for SPI Master Boot
Parameter Register
SPIBAUD
SPIFLG
SPIDMAC
IISPI
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Comment
SPI enabled
Master device
LSB first
32-bit SPI receive shift register word length
MISO enabled
Send zeros
Receive DMA enabled
Active low SPI clock
Toggle SPICLK at the beginning of the first bit
Figure
Initialization Value
0x64
0xFE01
0x0000 0007
IVT_START_ADDR
System Design
Figure
14-11.
Comment
SPICLK = PCLK/100
FLAG0 used as slave-select
Enable receive interrupt on completion
Start of block 0
14-12.
14-39
Advertisement
Table of Contents
