Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 213

the SPORT is configured in Loopback mode. This prevents contention
with the internal loopback data transfer.

Only transmit clock and transmit frame sync options may be used
in loopback mode—programs must ensure that the serial port is set
up correctly in the
not allowed. Only standard serial, left-justified, and I
support internal loopback. In loopback, each SPORT can be con-
figured as transmitter or receiver, and each one is capable of
generating an internal frame sync and clock.
Any of the four paired SPORTs can be set up to transmit or
receive, depending on their
Loopback Routing
The SPORTs support an internal loopback mode by using the SRU.
more information, see "Loop Back Routing" on page 5-30.
Buffer Hang Disable (BHD)
To support debugging buffer transfers, the ADSP-2136x processors have a
buffer hang disable (
sor core from detecting a buffer-related stall condition, permitting
debugging of this type of stall condition. For more information, see the
bit description on
BHD
Effect Latency
SPORT control register writes are internally completed at the end of five
core clock cycles. The newly written value to the SPORT control register
can be read back on the next cycle. After a write to a SPORT control reg-
ister, control and mode bit changes take effect in the second serial clock
cycle ( ).
SCLK
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
control registers. Multichannel mode is
SPCTLx
SPTRAN
) bit. When set (= 1), this bit prevents the proces-
BHD
on page 6-12.
Serial Ports
2
bit configurations
S modes
For
6-55