Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 500

Peripheral Registers
Table A-4. SPICTL Register Bit Descriptions (Cont'd)
Bit Name
3 GM
4 ISSEN
5 DMISO
6 Reserved
8–7 WL
9 MSBF
10 CPHASE
11 CLKPL
12 SPIMS
A-16
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Description
Get Data. When RXSPI is full, get data or discard incoming data.
0 = Discard incoming data
1 = Get more data, overwrites the previous data
Input Slave Select Enable. When enabled as a master,
error-detection input for the SPI in a multi-master environment. When this
bit is set and another SPI device asserts the
master then the current master releases the bus and configures it as slave. At
this point the ISSS-bit (SPIFLAG/B register) reflect the status of the
pin.
0 = Multi-master error detection disabled
1 = Multi-master error detection enabled
Note that /SPIDS pin is the chip select for SPI in slave mode.
Disable MISO Pin. Disables MISO as an output when a master wishes to
transmit to various slaves at one time (broadcast). Only one slave is allowed
to transmit data back to the master. Except for the slave from whom the mas-
ter wishes to receive, all other slaves should have this bit set.
0 = MISO enabled
1 = MISO disabled
Word L ength.
00 = 8 bits
01 = 16 bits
10 = 32 bits
Most Significant Byte First.
0 = LSB sent/received first
1 = MSB sent/received first
Clock Phase. Selects the transfer format.
0 = SPICLK starts toggling at the middle of 1st data bit
1 = SPICLK starts toggling at the start of 1st data bit
Clock Polarity.
0 = Active high SPICLK (SPICLK low is the idle state)
1 = Active low SPICLK (SPICLK high is the idle state)
SPI Master Select. Configures SPI module as master or slave.
0 = Device is a slave device
1 = Device is a master device
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
can serve as an
SPIDS
signal of the current SPI
SPIDS
SPIDS