Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 243

Multi Master Error (MME)
The bit (1) is set when the
MME
as a master is driven low by some other device in the system. This occurs
in multimaster systems when another device is also trying to be the master.
To enable this feature, set the
this error is detected, the following actions are taken:
1. The
SPIMS
interface as a slave.
2. The
SPIEN
system.
3. The
MME
4. An SPI interrupt is generated.
These four conditions persist until the
1-to-clear (W1C-type) software operation. Until the
SPI cannot be re-enabled, even as a slave. Hardware prevents the program
from setting either
When is cleared, the interrupt is deactivated. Before attempting to
MME
re-enable the SPI as a master, the state of the
checked to ensure that it is high; otherwise, once
another mode-fault error condition will immediately occur. The state of
the input pin is reflected in the input slave select status bit (bit 7) in the
register.
SPIFLG
As a result of
SPIEN
drivers ( ,
MOSI MISO
output pins revert to control by the processor flag I/O module registers.
This may cause contention on the slave-select lines if these lines are still
being driven by the processor. In order to ensure that the slave-select out-
put drivers are disabled once a
configure these pins as inputs by setting (= 1) the flag output select bits,
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
SPIDS
ISSEN
control bit in
SPICTL
control bit in
SPICTL
status bit in
SPISTAT
or
SPIEN SPIMS
and being cleared, the SPI data and clock pin
SPIMS
, and ) are disabled. However, the slave-select
SPICLK
MME
Serial Peripheral Interface Ports
input pin of a device that is enabled
bit in the
SPICTL
is cleared, configuring the SPI
is cleared, disabling the SPI
is set.
bit is cleared by a write
MME
MME
while is set.
MME
input pin should be
SPIDS
SPIEN
error occurs, the program must
register. As soon as
bit is cleared, the
and are set,
SPIMS
7-19