Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 462

Designing for High Frequency Operation
V SENSE
Vt=+1.25V
RESET
Figure 14-7. Reset Generator and Power Supply Monitor
Designing for High Frequency Operation
Because the processor must be able to operate at very high clock frequen-
cies, signal integrity and noise problems must be considered for circuit
board design and layout. The following sections discuss these topics and
suggest various techniques to use when designing and debugging target
systems.
All synchronous processor behavior is specified to
are encouraged to clock synchronous peripherals with this same clock
source (or a different low-skew output from the same clock driver).
14-28
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V DDEXT +3.3V
100nF
ADM706TAR
2 7
VCC
RST
4 5
PFO
PFI
1 8
WDO
MR
6 3
WDI GND
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
10µF
V DDEXT
RESET
a
IRQ0
ADSP-2136x
S
IRQ1
FLAG0
GND
CLKIN
100nF
. System designers