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Peripherals Routed Through the DAI
IDP Status Register (DAI_STAT0)
The
DAI_STAT0
Table A-23
is a read-only register. The state of all eight DMA channels is
reflected in the
ter). These bits are set once
data of that channel is transferred. Even if
goes low once the required number of data transfers occur. Furthermore,
if DMA through some channel is not intended, its
high.
31 30 29 28 27 26 25 24
IDP_FIFOSZ (31–28)
Number of Valid Data in IDP FIFO
IDP_DMA7_STAT
IDP_DMA6_STAT
IDP_DMA5_STAT
15 14 13 12
SRU_OVF7
SRU_OVF6
SRU_OVF5
SRU_OVF4
SRU_OVF3
SRU_OVF2
SRU_OVF1
SRU_OVF0
IDP Channel Overflow (Sticky)
Figure A-24. DAI_STAT0 Register
A-54
www.BDTIC.com/ADI
register, shown
Figure A-24
register (bits 24–17 of the
IDP_DMAx_STAT
IDP_DMA_EN
23 22 21 20 19 18 17 16
11 10
9
8
7
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
in and described in
is set and remain set until the last
is set (=1) this bit
IDP_DMA_EN
IDP_DMAx_STAT
IDP_DMA0_STAT
IDP_DMA1_STAT
IDP_DMA2_STAT
IDP_DMA3_STAT
IDP_DMA4_STAT
DMA Active Status for
IDP Channel
6
5
4
3
2
1
0
regis-
DAI_STAT
bit goes
SRU_PING0_STAT
SRU_PING1_STAT
SRU_PING2_STAT
SRU_PING3_STAT
SRU_PING4_STAT
SRU_PING5_STAT
SRU_PING6_STAT
SRU_PING7_STAT
Ping-pong DMA
Channel Status
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