Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 536

Peripherals Routed Through the DAI
Table A-21. IDP_PP_CTL Register Bit Descriptions (Cont'd)
Bit Name
28–27 IDP_PDAP_PACKING
29 IDP_PDAP_CLKEDGE
30 IDP_PDAP_RESET
31 IDP_PDAP_EN
A-52
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Description
Packing. Selects PDAP packing mode. These bits
mask parallel sub words from the 20 parallel
input signals and packs them into a 32-bit word. The
bit field indicates how data is packed. Selection of
packing mode is made based on the
application.
00 = 8- to 32-bit packing
01 = (11, 11, 10) to 32-bit packing
10 = 16- to 32-bit packing
11 = 20- to 32-bit packing. 12 LSBs are set to 0
Note for input data width less than 20-bits, inputs are
aligned to MSB pins.
PDAP (Rising or Falling) Clock Edge.
Setting this bit (= 1) causes the data to latch on the
falling edge (PDAP_CLK_I signal). Clearing this bit
(= 0) causes data to latch on the rising edge (default).
Notice that in all four packing modes described, data
is read on a clock edge, but the specific edge used (ris-
ing or falling) is not indicated.
0 = Data is latched on the rising edge
1 = Data is latched on the falling edge
PDAP Reset. A reset clears any data in the packing
unit waiting to get latched into the IDP FIFO. This
bit causes the reset circuit to strobe when asserted,
and then automatically clears. Therefore, this bit
always returns a value of zero when read.
PDAP Enable.
0 = Disconnects all PDAP inputs (data/control) from
use as parallel input channel.
1 = Connects all PDAP inputs (data/control) from use
as parallel input channel.
IDP channel 0 cannot be used as a serial input port
with this setting.
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors