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S/PDIF Receiver
over sampling clock division ratio, SCDF mode select and enable, serial
data input format select and validity and channel status buffer selects. By
default, all the bits in this register are zero.
If the channel status or validity buffer needs to be enabled (after the SRU
programming is complete), first write to the buffers with the required data
and then enable the buffers by setting
Setting
DIT_AUTO
frame) being generated internally. Also use this register to write other con-
trol values such as
setting the
DIT_EN
Channel Status Registers (DITCHANAx/Bx)
These registers provide status information for transmitter subframe A and
B. The first five bytes of the channel status may be written all at once to
the control registers for both A and B channels. As the data is serialized
and transmitted, the appropriate bit is inserted into the channel status area
of the 192-word frame. Note these registers are used in standalone mode
only.
S/PDIF Receiver
The S/PDIF receiver
digital application interface standards including IEC-60958, IEC-61937,
AES3, and AES11. These standards define a group of protocols that are
commonly associated with the S/PDIF interface standard defined by
AES3, which was developed and is maintained by the Audio Engineering
Society. The AES3 standard effectively defines the data and status bit
structure of an S/PDIF stream. AES3-compliant data is sometimes
referred to as AES/EBU compliant. This term highlights the adoption of
the AES3 standard by the European Broadcasting Union.
11-10
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bit also results in the block start bit (indicating start of a
,
DIT_SMODEIN
DIT_FREQ
bit.
(Figure
11-8) is compliant with all common serial
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
(bit 9 of
DIT_AUTO
DITCTL
, and enable the transmitter by
register).
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