Table of Contents
Advertisement
31 30 29 28 27 26 25 24
SPORT5_CLK_I (29–25)
Serial Port 5 Clock Input
15 14 13 12
SPORT3_CLK_I (19–15)
SPORT2_CLK_I (14–10)
Serial Port 2 Clock Input
Figure A-40. SRU_CLK0 Register
31 30 29 28 27 26 25 24
SRC2_CLK_OP_I (29–25)
Sample Rate Converter 2
Clock Output Input
15 14 13 12
SRC1_CLK_OP_I (19–15)
Sample Rate Converter 1
Clock Output Input
SRC1_CLK_IP_I (14–10)
Sample Rate Converter 1
Clock Input Input
Figure A-41. SRU_CLK1 Register
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
23 22 21 20 19 18 17 16
11 10
9
8
7
6
5
4
23 22 21 20 19 18 17 16
11 10
9
8
7
6
5
4
Registers Reference
SPORT3_CLK_I (19–15)
Serial Port 3 Clock Input
SPORT4_CLK_I (24–20)
Serial Port 4 Clock Input
3
2
1
0
SPORT0_CLK_I (4–0)
Serial Port 0 Clock Input
SPORT1_CLK_I (9–5)
Serial Port 1 Clock Input
SRC1_CLK_OP_I (19–15)
Sample Rate Converter 1
Clock Output Input
SRC2_CLK_IP_I (24–20)
Sample Rate Converter 2
Clock Input Input
3
2
1
0
SRC0_CLK_IP_I (4–0)
Sample Rate Converter 0
Clock Input Input
SRC0_CLK_OP_I (9–5)
Sample Rate Converter 0
Clock Output Input
A-81
Advertisement
Table of Contents
