Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 523

Table A-16. SPCTLx Register Bit Descriptions (I
Left-Justified) (Cont'd)
Bit Name
29 DERR_A
31–30 DXS_A
31 30 29 28 27 26 25 24
RXS_A/TXS_A (31–30)
Data Buffer Channel A Status
ROVF_A/TUVF_A
Channel A overflow/underflow
status (sticky)
RXS_B/TXS_B (28–27)
Data Buffer Channel B Status
ROVF_B/TUVF_B
Channel B overflow/underflow
status (sticky)
BHD
Buffer Hang Disable
15 14 13 12
IMFS
Internally Generated Mul-
tichannel Frame Sync
CKRE
Active Clock Edge for Data
and Frame Sync Sampling
OPMODE
SPORT Operation Mode
ICLK
Internally Generated Clock
Figure A-17. SPCTLx Register – Multichannel Mode
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Description
Channel A Error Status (sticky, read-only). Refer to DERR_B
Channel A Data Buffer Status (read-only). Refer to DXS_B
23 22 21 20 19 18 17 16
11 10 9 8 7 6
Registers Reference
2
S,
LMFS/LTDV
Active Low
Transmit Data Valid
SDEN_A
Receive DMA
Channel A Enable
SCHEN_A
Receive DMA Channel A
Chaining Enable
SDEN_B
Receive DMA Channel B
Enable
SCHEN_B
Receive DMA Channel B
Chaining Enable
5 4 3 2 1 0
DTYPE (2–1)
Data Type
LSBF
Serial Word Bit Order
SLEN (8–4)
Serial Word Length-1
PACK
16/32 Packing
A-39