Interrupts - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

Table of Contents

Interrupts

• While a DMA transfer is active, the core may only write the

isters or other bits in

parallel port to malfunction.

• Core reads of the FIFO register during a DMA operation are

allowed but do not affect the status of the FIFO.

is cleared while a transfer is underway (whether core or

DMA driven), the current external bus cycle (

cycle) completes but no further exte rnal bus cycles occur. Disabling

the parallel port clears the data in the

• Core reads and writes to the

tus of the FIFO when DMA is not active. This happens even when

the parallel port is disabled.

• For core-driven transfers over the parallel port, the

ters need to be initialized before accessing the

• To change any access related control bits in the

disable the parallel port by clearing the

ter, then read the

external interface of parallel port is an idle state, and finally write

The parallel port has one interrupt signal (PPI) which is generated for all

core or DMA related operations.

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. Accessing any of the DMA parameter reg-

during an active transfer will cause the

registers are not used. Only the

ADSP-2136x SHARC Processor Hardware Reference

for the ADSP-21362/3/4/5/6 Processors

cycle or data

registers update the sta-