Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 452

Pin Multiplexing
Table 14-5. Multiplexing Registers and Bits (Cont'd)
Registers Used
IDP_PP_CTL
PPCTL
FLAG3–0 Pins
As described Table 14-5
multiplex around the following four interfaces.
• FLAGS (input/output)
• Interrupts (input)
• Core timer (output)
• SPI (output, slave selects)
The pins allow single bit signaling between the processor and
FLAG3-0
other devices. For example, the processor can raise an output flag to inter-
rupt a host processor. Each flag pin can be programmed to be either an
input or output. In addition, many processor instructions can be
conditioned on a flag's input value, enabling efficient communication and
synchronization between multiple processors or other interfaces.
The flags are bidirectional pins and all have the same functionality. The
bits in the
FLG3-0
For more information, see the SHARC Processor Programming Reference.
The processor's external interrupt pins, and core timer pin can be used to
send and receive control signals to and from other devices in the system.
The pins are mapped on the
IRQ2-0
timer) is mapped on the
are received on the
require the processor to perform some task on demand. A mem-
ory-mapped peripheral, for example, can use an interrupt to alert the
14-18
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Bits Used
IDP_PP_SELECT, PDAP_SEL
PPEN
and shown in
register program the direction of each flag pin.
FLAGS
FLAG2-0
pin. Hardware interrupt signals (
FLAG3
pins. Interrupts can come from devices that
FLAG2-0
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
Figure 14-3, The
FLAG3-0
pins and the
TMREXP
pins can
pin (core
)
IRQ2-0