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BAUD Rate Register (SPIBAUDx)
For master devices, the clock rate is determined by the 15-bit value of the
baud rate registers (
the value in the
"SPI Baud Rate Registers (SPIBAUD, SPIBAUDB)" on page A-20.
Table 7-5. SPI BAUD Rate Settings
BAUDR Bit Setting
0
1
2
3
4
32,767 (0x7FFF)
DMA Control Register (SPIDMACx)
This register contains the error status bits (
). These bits are set when an error occurs during a DMA transfer.
SPIERRS
The (
) bit is set if any of the
SPIERRS
interrupt can be generated with the (
Data Transfer Types
The SPI is capable of transferring data via the core and DMA. The follow-
ing sections describe these transfer types.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
) as shown in
SPIBAUDx
register is ignored.
SPIBAUDx
Divider
N/A
8
16
24
32
262136
Serial Peripheral Interface Ports
Table
7-5. For slave devices,
For more information, see
SPICLK (PCLK = 167 MHz)
N/A
41.7 MHz
20.8 MHz
13.9 MHz
10.4 MHz
1.3 KHz
,
SPIMME
SPIUNF
,
,
SPIMME
SPIUNF
SPIOVF
) bit to respond to these errors.
INTERR
,
and
SPIOVF
bits is set. An
7-21
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