Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 174

Registers
Bits 31–30 (
RXS_A)
cate the status of the channel's receive buffer contents as follows: 00 =
buffer empty, 01 = reserved, 10 = buffer partially full, 11 = buffer full.
If your program causes the core processor to attempt to read from an
empty receive buffer or to write to a full transmit buffer, the access is
delayed until the buffer is accessed by the external I/O device. This delay
is called a core processor hang. If you do not know if the core processor
can access the receive or transmit buffer without a hang, the buffer's status
should be read first (in
The status bits in
core processor even when the serial port is disabled. Programs should dis-
able the serial port when writing to the receive buffer or reading from the
transmit buffer.
When the SPORT is configured as a transmitter, the
transmit underflow status. As a transmitter, if
indicate whether the
source) occurred while the
whenever the SPORT is required to transmit and the transmit buffer is
empty. The SPORTs transmit data whenever they detect a
signal.
• 0 = No
SPORTx_FS
• 1 =
SPORTx_FS
When the SPORT is configured as a receiver, the
receive overflow status. As a receiver, it indicates when the channel has
received new data while the
ing data.
• 0 = No new data while
• 1 = New data while
6-16
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and bits 28–27 (
RXS_B)
) to determine if the access can be made.
SPCTLx
are updated during reads and writes from the
SPCTLx
signal (from an internal or external
SPORTx_FS
buffer was empty. If
DXS
signal occurred while
signal occurred while
buffer is full. New data overwrites exist-
RXS_A
RXSPxA
/ buffer is full.
RXSPxA B
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
in the
SPCTLx
DERR_x
= 1, the
FSR
= 0,
FSR
/
TXSPxA B
/ buffer is empty.
TXSPxA B
DERR_x
/ buffer is full.
B
registers indi-
bits provide
bits
DERR_x
is set
DERR_x
SPORTx_FS
buffer is empty.
bits provide