Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 265

Table of Contents

shift register. DMA interrupts are latched when the I/O processor moves

the last word from memory to the peripheral. For the SPI, this means that

the SPI "DMA complete" interrupt is latched when there are six words

remaining to be transmitted (four in the FIFO, one in the

and one being shifted out of the shift register). To disable the SPI port

after a DMA transmit operation, use the following steps:

1. Wait for the DMA FIFO to empty. This is done when the

bits (bits 13–12 in the

2. Wait for the

bit, (bit 3) in the

When stopping receive DMA transfers, it is recommended that

programs follow the SPI disable steps provided in

Receive to Receive/Transmit DMA"

3. Wait for the SPI shift register to finish transferring the last word.

This is done when the

becomes one.

4. Disable the SPI ports by setting the

registers to zero.

Switching from Transmit To Transmit/Receive DMA

The following sequence details the steps for switching from transmit to

receive DMA.

With disabled SPI:

1. Write 0x00 to the

SPI also clears the

2. Disable DMA by writing 0x00 to the

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

Serial Peripheral Interface Ports

registers to empty. This is done when the

registers becomes zero.

bit (bit 0) of the

registers to disable SPI. Disabling the

registers) become zero.

"Switching from

bit (bit 0) of the

registers and the buffer status.