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cycle. In double update mode, the
the mid-point of the PWM cycle.
After reset, all four enable bits of the
that all PWM outputs are enabled by default.
Crossover Mode
The
PWMSEG3–0
for each PWM output (see
SEGx)" on page
signals, the high-side PWM signal from the timing unit (for example,
is diverted to the associated low side output of the output control unit so
that the signal ultimately appears at the
The corresponding low side output of the timing unit is also diverted to
the complementary high side output of the output control unit so that the
signal appears at the
cleared so that the crossover mode is disabled on both pairs of PWM sig-
nals. Even though crossover is considered an output control feature, dead
time insertion occurs after crossover transitions to eliminate
shoot-through safety issues.
Note that crossover mode does not work if:
1. One signal of
2.
and
PWM_AL
settings from
In other words, both
enabled and both should have same polarity for proper operation of
cross-over mode.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
registers contain two bits (
"PWM Output Disable Registers (PWM-
A-27). If crossover mode is enabled for any pair of PWM
pin. Following a reset, the two crossover bits are
AH
–
PWM_AL
PWM_AH
or
PWM_AH
PWM_BL
registers.
PWMPOLx
and
PWM_AL
PWM_AH
Pulse Width Modulation
register can also be updated at
PWMSEG
register are cleared so
PWMSEG
and
PWM_AXOV
pin.
AL
or
–
PWM_BL
PWM_BH
and
have different polarity
PWM_BH
or
and
PWM_BL
), one
PWM_BXOV
)
AH
is disabled.
should be
PWM_BH
10-23
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