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Because polling uses processor core resources, it is not as efficient
as an interrupt-driven system. Also note that polling the DMA sta-
tus registers reduces I/O bandwidth (core higher priority like I/O,
see
"IOP Performance" on page
The DMA controllers in the ADSP-2136x processor maintain the status
information of each channel for the different DMA modes in each of the
peripherals registers:
• PPCTL (Standard and chaining)
• SPMCTLxy (Standard and chaining)
• SPIDMAC, SPIDMACB (Standard and chaining)
• DAI_STAT (Standard, Ping-pong)
• MTMCTL (Standard)
Note that there is a one cycle latency between a change in DMA channel
status and the status update in the corresponding register.
Standard DMA Status
By starting DMA, the related DMA status bit is set and cleared at the end
of the DMA.
Chaining DMA Status
Two status bits are available for chaining status—one bit for DMA status
and one bit for chain loading DMA status. When a program starts a
chained DMA, chain loading is triggered, and the related chain loading
status bit is set. After the TCB loading completes, its status bit is cleared
and the DMA status bit is set. This scenario is repeated until the chain
pointer reaches zero. Note that there is a one cycle latency between a
change in DMA channel status and the st a tus update in the corresponding
register.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
I/O Processor
2-35).
2-29
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