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Parallel Data Acquisition Port (PDAP)
Mode 10 (Packing by 2)
Mode 10 moves data in two cycles. Each input word can be up to 16 bits
wide.
• On clock edge 1, bits 19–4 are moved to bits 15–0 (16 bits)
• On clock edge 2, bits 19–4 are moved to bits 31–16 (16 bits)
This mode sends one packed 32-bit word to FIFO for every two input
clock cycles—the DMA transfer rate is one-half the PDAP input clock
rate.
Mode 01 (Packing by 3)
Mode 01 packs three acquired samples together. Since the resulting 32-bit
word is not divisible by three, up to ten bits are acquired on the first clock
edge and up to eleven bits are acquired on each of the second and third
clock edges:
• On clock edge 1, bits 19–10 are moved to bits 9–0 (10 bits)
• On clock edge 2, bits 19–9 are moved to bits 20–10 (11 bits)
• On clock edge 3, bits 19–9 are moved to bits 31–21 (11 bits)
This mode sends one packed 32-bit word to FIFO for every three input
clock cycles—the DMA transfer rate is one-third the PDAP input clock
rate.
Mode 00 (Packing by 4)
Mode 00 moves data in four cycles. Each input word can be up to eight
bits wide.
• On clock edge 1, bits 19–12 are moved to bits 7–0
• On clock edge 2, bits 19–12 are moved to bits 15–8
8-14
www.BDTIC.com/ADI
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
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