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A-107, provide status information for the IDP/PDAP DMA chan-
nels. The
DAI_PIN_PULLUP
to enable/disable pull-up resistors.
Digital Applications Interface Status Register (DAI_STAT)
The
register is a read-only register. The state of all eight DMA
DAI_STAT
channels is reflected in the
register). These bits are set once
DAI_STAT
until the last data of that channel is transferred. Even if
(=1) this bit goes low once the required number of data transfers occur.
Furthermore, if DMA through some channel is not intended, its
IDP_DMAx_STAT
31 30 29 28 27 26 25 24
IDP_FIFOSZ
Number of Valid Data in IDP FIFO
IDP_DMA7_STAT
IDP_DMA6_STAT
IDP_DMA5_STAT
15 14 13 12
SRU_OVF7
SRU_OVF6
SRU_OVF5
SRU_OVF4
SRU_OVF3
SRU_OVF2
SRU_OVF1
SRU_OVF0
IDP Channel Overflow (Sticky)
Figure A-39. DAI_STAT Register
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
register, shown in
IDP_DMAx_STAT
bit goes high.
23 22 21 20 19 18 17 16
11 10
9
8
7
Registers Reference
Figure
A-66, allows programs
register (bits 24–17 of the
is set and remain set
IDP_DMA_EN
IDP_DMA0_STAT
IDP_DMA1_STAT
IDP_DMA2_STAT
IDP_DMA3_STAT
IDP_DMA4_STAT
DMA Active Status for
IDP Channel
6
5
4
3
2
1
0
SRU_PING0_STAT
SRU_PING1_STAT
SRU_PING2_STAT
SRU_PING3_STAT
SRU_PING4_STAT
SRU_PING5_STAT
SRU_PING6_STAT
SRU_PING7_STAT
is set
IDP_DMA_EN
Ping-pong DMA
Channel Status
A-79
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