Table of Contents
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Index
biphase
encoded audio stream, 11-11,
routing data,
11-4
S/PDIF receiver data register (DIR_I),
11-13
bits See peripheral specific bits, bits by
name or acronym
block diagram
IDP,
8-4
IDP channel 0,
8-10
parallel port,
4-3
PLL,
14-5
PWM,
10-3
S/PDIF transmitter,
11-5
SPI,
7-6
SPORTs,
6-3
SRC,
12-5
system, processor,
1-3
boolean operator
OR, 8-30,
11-21
booting
boot kernal,
14-49
bootstrap loading,
14-32
DMA use in,
2-2
hardware use,
14-32
IVT addresses,
14-35
process,
14-32
SPI master mode,
14-38
SPI packing,
14-42
SPI slave mode,
14-41
boot memory select pin (BMS) not used,
4-3
buffer
addressing,
2-18
data,
2-9
DMA count,
2-4
interrupts, 2-27,
4-15
parallel port operation,
SPORT data,
6-1
stalls, core, 2-33,
4-17
I-2
www.BDTIC.com/ADI
11-13
4-11
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
buffer
TCB allocation,
2-21
buffer enable (DIT_CHANBUF) bit
(S/PDIF),
11-10
buffer hang disable (BHD) bit, 6-55, A-34,
A-38,
A-41
buses
access through I/O processor,
ALE cycles and,
4-20
contention,
7-37
contention in SPORTs,
determining parallel port cycles,
external, 4-16, 4-25,
A-13
external parallel,
4-12
granting,
7-24
hold cycle enable (PPBHC) bit,
2
I
S and,
C-3
I/O address (IOA),
2-18
I/O data (IOD), 2-3, 2-14,
I/O processor (IOP), 2-3, 2-14,
packing sequence,
4-6
parallel port,
4-1
parallel port bus hold cycle enable
(PPBHC) bit,
4-8
parallel port bus hold cycle enable
(PPBHC) bits,
A-12
parallel port bus status (PPBS) bit, 4-16,
A-13
parallel port pins,
4-8
unpacking sequence,
4-7
bypass as a one-shot (strobe pulse),
C
capacitors, bypass, decoupling,
center-aligned paired PWM
double-update mode,
single-update mode,
10-14
chain assignment, I/O processor,
(continued)
2-34
6-43
4-17
4-17
7-37
6-21
13-14
14-29
10-16
2-22
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