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Subject to the maximum VCO frequency, the PLL supports a wide range
of multiplier ratios of the input clock,
plication range, the processor uses a combination of programmable
multipliers in the PLL feedback circuit and output configuration blocks.
The power management control register (
the PLL. For details, see
(PMCTL)" on page
INPUT CLOCK
CLKIN
DIVIDER
INDIV
PLLM or CLK_CFG[1:0]
BYPASS
PLLD
Figure 14-1. PLL Block Diagram
Input Clock
The processor receives its clock input on the
can be driven from:
• an external crystal oscillator (connected to the
• a crystal (connected between the
The processor uses an on-chip, phase-locked loop (PLL) to generate its
internal clock, which is a multiple of the
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
CLKIN
"Power Management Control Register
A-6.
PHASE
LOOP
DETECT
FILTER
FEEDBACK
DIVIDER
System Design
. To achieve this wide multi-
) governs the operation of
PMCTL
VCO
OUTPUT
CLOCK
GENERATOR
pin. As a source,
CLKIN
CLKIN
and
pins)
XTAL
CLKIN
frequency. Because the
CLKIN
CCLK
PCLK
(1/2 CCLK)
CLKIN
pin)
14-5
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