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• DMA transfers to and from on-chip and off-chip memory. Each
SPORT can automatically receive or transmit an entire block of
data both on- and off-chip.
• Chained DMA operations for multiple data blocks, see
Chaining" on page
• DMA Chain insertion mode allows the SPORTs to change DMA
priority during chaining, see
on page
• Data words between 3 and 32 bits inlength, either most significant
bit (MSB) first or least significant bit (LSB) first. Words must be
between 8 and 32 bits in length for I
• 128-channel TDM is supported in multichannel mode operation,
useful for H.100/H.110 and other telephony interfaces described
in
"Multichannel Operation" on page
• μ-law and A-law compression/decompression hardware compand-
ing on transmitted and received words when the SPORT operates
in TDM mode.
Receive comparison and 2-dimensional DMA are not supported in
the ADSP-2136x processor.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
2-20.
6-57.
"Enter DMA Chain Insertion Mode"
2
S and left-justified mode.
6-40.
Serial Ports
"DMA
6-5
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