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sample rates and provides the RAM and ROM start addresses
SRCx_FS_OP
for the start of the FIR filter convolution.
Unlike other peripherals, the sample rate converters own local
memories (RAM and ROM) which arededicated for the purpose of
sample rate conversion only.
The master clock input (
clock (
PCLK
Also note that the matched phase mode only applies to the
ADSP-21364 sample rate converter. For all other SHARC proces-
sors, the SRC sends zeros at the LSB eight bits instead of the
matched phase information when 32-bit clock is provided.
SRCx_FS_IP_I
SRCx_CLK_IP_I
SRCx_DAT_IP_I
SERIAL
INPUT
SRCx_TDM_IP_O
PORT
HARD MUTE IN BIT
SMODE BIT
MCLK
Figure 12-1. Sample Rate Converter Block Diagram
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Asynchronous Sample Rate Converter
MCLK
) divided by 4. Therefore,
DE-EMPHASIS
FILTER
DE-EMPHASIS BITS
SMODE OUT BITS
WLENGTH OUT BITS
DITHER BITS
MATCHED PHASED MODE BITS
) shown in
Figure 12-1
=
MCLK
PCLK
SAMPLE
RATE
MUTE OUT BITS
CONVERTER
MUTE IN BITS
SRC RATIO BITS
SRCx_DAT_OP_O
SRCx_FS_OP_I
SERIAL
OUTPUT
SRCx_CLK_OP_I
PORT
SRCx_TDM_OP_I
is peripheral
÷ 4.
12-5
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