Parallel Port Effect Latency; Programming Model - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

Table of Contents

• When the DMA external modifier is set to zero, (

address does not change after the first cycle, therefore an

is only inserted on the first cycle. In this case, the 16-bit port can

run twice as fast as the 8-bit port, as the overhead for

zero. This is convenient when interfacing to high speed 16-bit

FIFO-based devices, including A/D and D/A converters.

• In situations where a majority of address accesses are non-sequen-

tial and cross 256 byte boundaries, the overhead of the

in the 8-bit mode approaches 20%

the 16-bit memory can provide a 40% speed advantage over the

Parallel Port Effect Latency

grams write to this register in cycle N, the new settings are not in effect

until cycle N + 2. Avoid sampling

For read operations (

(=1), the parallel port fetches two 32-bit data words from the external byte

address indicated by

when the core reads (empties)

The following sections provide information for setting up and using the

parallel port.

This can be realized by recalling that four bytes must be packed/unpacked into a single 32-bit word.

For example when a 32-bit word is written/read, there is a single ALE cycle inserted per four consecu-

tive addresses. This results in: (N/4 ALE cycles)/(N accesses + N/4 ALE cycles) x 100% = 20%.

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

=0), two core clock cycles after

. Subsequently, additional data is fetched only

. In this particular situation,

until at least two cycles after the

Parallel Port