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31 30 29 28 27 26 25 24
PCG_SYNC_CLKA_I (29–25)
Precision Clock Generator
Clock A Sync Input
15 14 13 12
SPIB_CLK_I (19–15)
SPDIF_EXTPLLCLK_I (14–10)
External 512 x FS PLL Clock Input
Setting SRU_CLK4 4–0 = 28 connects PCG_EXTA_I to logic low, not to PCG_CLKA_O.
Setting SRU_CLK4 9–5 = 29 connects PCG_EXTB_I to logic low, not to PCG_CLKB_O.
Figure A-44. SRU_CLK4 Register
Table A-42. Group A Sources – Serial Clock
Selection Code
00000 (0x0)
00001 (0x1)
00010 (0x2)
00011 (0x3)
00100 (0x4)
00101 (0x5)
00110 (0x6)
00111 (0x7)
01000 (0x8)
01001 (0x9)
01010 (0xA)
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
23 22 21 20 19 18 17 16
11 10
9
8
7
Source Signal
DAI_PB01_O
DAI_PB02_O
DAI_PB03_O
DAI_PB04_O
DAI_PB05_O
DAI_PB06_O
DAI_PB07_O
DAI_PB08_O
DAI_PB09_O
DAI_PB10_O
DAI_PB11_O
Registers Reference
SPIB_CLK_I (con't) (19–15)
Serial Peripheral Interface
2 Clock
PCG_SYNC_CLKB_I (24–20)
Precision Clock Generator
Clock B Sync Input
6
5
4
3
2
1
0
PCG_EXTA_I (4–0)
Precision Clock Generator
External Clock A Input
PCG_EXTB_I (9–5)
Precision Clock Generator
External Clock B Input
Description (Source Selection)
Pin buffer 1
Pin buffer 2
Pin buffer 3
Pin buffer 4
Pin buffer 5
Pin buffer 6
Pin buffer 7
Pin buffer 8
Pin buffer 9
Pin buffer 10
Pin buffer 11
A-83
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