Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 252

Table of Contents

To maintain software compatibility with other SPI devices (HC-11), the

SPI transfer finished bit (

have slightly different behavior from that of other commercially available

devices. For a slave device,

is set one-half (0.5) of the

edge, regardless of

bit is set. In general,

quently before new data has been latched into the

be set (after SPIF is set) before reading the

The following section describes SPI operations using both the core and

direct memory access (DMA).

Interrupt Sources

The SPI ports can generate interrupts in five different situations. During

core-driven transfers, an SPI interrupt is triggered:

from the core

(transfer initiation and interrupt) register determines whether

the interrupt is based on the

If configured to generate an interrupt when

00), the interrupt will be active 1

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) is also available for polling. This bit may

is set at the same time as

. The baud rate determines when the

is set after

bit is set before the

= 3, the processor must wait for the

is set before

buffer has the capacity to accept another word

buffer contains a valid word to be retrieved by the

ADSP-2136x SHARC Processor Hardware Reference

for the ADSP-21362/3/4/5/6 Processors

period after the last

, but at the lowest baud rate

bit, and conse-

buffer. Therefore,

buffer. For larger

buffer status.

cycle after the

. For a master