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transmitting the fixed number of words. The transmission of this
dummy word toggles
of the dummy word is not required when the I
port.
2
I
S Mode Timing Control Bits
Several bits in the
operation:
• Late frame sync (
• Operation mode (
• Frame sync channel first (
• Master mode enable (
• Word length (
• Channel enable (
2
I
S mode is simply a subset of the left-justified mode which can be
invoked by setting
that in I
Selecting Transmit and Receive Channel Order (L_FIRST)
In master and slave modes, it is possible to configure the I
which each SPORT channel transmits or receives first. By default, the
SPORT channels transmit and receive on the right I
2
left and right I
To select the channel order, set the
on the left channel first, or clear the
receive on the right channel first.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
SPORTx_FS
register enable and configure I
SPCTLx
= 0, I
LAFS
= 1, I
OPMODE
L_FIRST
)
MSTR
, 8–32 bits)
SLEN
or
SPEN_A
= 1,
OPMODE
2
S mode, the data is delayed by one
S channels are time-duplexed data channels.
, generating an edge. Transmission
2
S mode)
2
S mode)
2
= 1, I
S mode)
)
SPEN_B
= 0, and
LAFS
L_FIRST
SCLK
2
bit (= 1) to transmit or re ceive
L_FIRST
bit (= 0) to transmit or
L_FIRST
Serial Ports
2
S receiver is a serial
2
S mode
= 1. Note
cycle
2
S channel to
S channel first. The
6-39
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