Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 256

Debug Features
This is shown as:
T3 = 0.5 SPI clock period
T4 = 1.5 SPI clock period + T3
For a master device with
slave-select output is inactive (high) for at least one-half the
period. In this case, T1 and T2 are each always be equal to one-half the
period.
SPICLK
SPI CLK
CPHASE =0
SPIDS
TO SLAVE
Figure 7-6. SPICLK Timing
Debug Features
The following sections provide information on features that help in
debugging SPI software.
Shadow Register
A shadow register for the receive data buffer,
debugging software. This register,
from , but its contents are identical to that of
SPIRX
read from core, the
(if = 00). No such hardware action occurs when the shadow register
TIMOD
is read.
SPIRX_SHADOW
core.
7-32
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= 0 or
CPHASE
T1 T2
T3
T4
SPIRX_SHADOW
bit is cleared and an SPI transfer may be initiated
RXS
is a read-only register and only accessible by the
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
= 1, this means that the
CPHASE
, is available for use in
SPIRX
, is at a different address
. When
SPIRX
SPICLK
is
SPIRX