Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 512

Peripheral Registers
Table A-12. PWMSEGx Register Bit Descriptions (Cont'd)
Bit Name
4 PWM_BXOV
5 PWM_AXOV
15–6 Reserved
PWM Polarity Select Registers (PWMPOLx)
These 16-bit registers, shown
control the polarity of the four PWM groups which can be set to either
active high or active low. Note that bit 1 has priority over bit 0, bit 3 over
bit 2 and so on.
15 14 13 12
PWM_POL0BH
Channel B High Polarity 1
PWM_POL1BH
Channel B High Polarity 0
PWM_POL0BL
Channel B Low Polarity 1
PWM_POL1BL
Channel B Low Polarity 0
Figure A-14. PWMPOLx Register
Table A-13. PWMPOLx Register Bit Descriptions
Bit Name
0 PWM_POL1AL
1 PWM_POL0AL
A-28
www.BDTIC.com/ADI
Description
B Signal Pair Crossover Enable. Enable cross over mode for the
PWM_BH and PWM_BL signal pair.
0 = Disable
1 = Enable
A Signal Pair Crossover Enable. Enable cross over mode for the
PWM_AH and PWM_AL signal pair.
0 = Disable
1 = Enable
inFigure A-14
11 10 9 8 7 6
Description
Write 1 to set channel A low polarity 1
Write to set channel A low polarity 0
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
and described in
5 4 3 2 1 0
PWM_POL1AL
Channel A Low Polarity 1
PWM_POL0AL
Channel A Low Polarity 0
PWM_POL1AH
Channel A High Polarity 1
PWM_POL0AH
Channel A High Polarity 0
Table A-13,