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Peripherals Routed Through the DAI
Table A-16. SPCTLx Register Bit Descriptions (I
Left-Justified) (Cont'd)
Bit
Name
21
SCHEN_B
22
Reserved
23
BHD
24
SPEN_B
25
SPTRAN
26
DERR_B
28–27
DXS_B
A-38
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Description
Enable Channel B Serial Port DMA Chaining.
0 = Disable serial port channel B DMA chaining
1 = Enable serial port channel B DMA chaining
Buffer Hang Disable.
0 = Indicates a core stall. The core stalls when it tries to write to a full
transmit buffer or read an empty receive buffer FIFO.
1 = Ignore a core hang
Enable Channel B Serial Port.
0 = Serial port A channel disabled
1 = Serial port A channel enabled
Data Direction Control. This bit controls the data direction of the
serial port channel A and B signals.
0 = SPORT is configured to receive on both channels A and B. When
configured to receive, the RXSPxA and RXSPxB buffers are activated,
while the receive shift registers are controlled by SPORTx_CLK and
SPORTx_FS. The TXSPxA and TXSPxB buffers are inactive.
1 = SPORT is configured to transmit on both channels A and B. When
configured to transmit, the TXSPxA and TXSPxB buffers are activated,
while the transmit shift registers are controlled by SPORTx_CLK and
SPORTx_FS. The RXSPxA and RXSPxB buffers are inactive.
Channel B Error Status (sticky, read-only). Indicates if the serial trans-
mit operation has underflowed or a receive operation has overflowed in
the channel B data buffer.
The error status bit (DERR_B) are set when the SPORTx_FS signal
occurs from either an external or internal source while the TXSPxB
buffer is empty. The internally-generated SPORTx_FS signal may be
suppressed whenever TXSPxB is empty by clearing the DIFS control bit
when SPTRAN = 1.
Channel B Data Buffer Status (read-only). Indicates the status of the
serial port's channel B data buffer (RXSPxB or TXSPxB) as follows:
00 = Empty
10 = Partially full
11 = Full
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
2
S,
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