Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 250

Data Transfer Types

Writing an address to the
chained DMA sequence unless the
, and
IMSPIB
the SPI port is enabled, and SPI DMA chaining is enabled.
Core and DMA Transfers
When the SPI DMA engine is configured for transmitting:
1. The receive interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the receive path.
Similarly, when the SPI DMA engine is configured for receiving:
1. The transmit interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the transmit path.
Changing Configuration
Programs should take the following precautions when changing SPI
configurations.
• The SPI configuration must not be changed during a data transfer.
• Change the clock polarity only when no slaves are selected.
• Change the SPI configuration when
operating as a master in a multislave system, and there are slaves
that require different data or clock formats, then the master SPI
should be disabled, reconfigured, and then re-enabled.
7-26
www.BDTIC.com/ADI
CPSPIx
registers are initialized, SPI DMA is enabled,
CSPIB
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
, registers does not begin a
, ,
IISPI IMSPI CSPI
= 0. For example, if
SPIEN
, ,
IISPIB