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TDM Mode
L/RCLK
BCLK
SLOT 1
DATA
LEFT 0
Figure C-2. Packed TDM Mode
MOST Mode
A special packed TDM mode is available that allows four channels to be
fit into a space of 64-bit clock cycles. This mode is called packed TDM4
mode, or MOST™ mode. MOST (MediaOriented Systems Transport) is
a networking standard intended for interconnecting multimedia compo-
nents in automobiles and other vehicles. Many integrated circuits
intended to interface with a MOST bus use a packed TDM4 data format.
Figure C-3
illustrates a word length of 16 bits for a timing diagram of the
packed TDM4 mode. This figure is shown with a negative
negative
LRCLK
serial data must be delayed by one bit clock from the start of the frame
2
(I
S position).
C-8
www.BDTIC.com/ADI
SLOT 2
SLOT 3
BLANK SLOT
LEFT 1
LEFT 2
4 SCLK
BCLK
MSB
20-BIT DATA
MSB
–1
MSB
16-BIT DATA
MSB
–1
polarity, and an MSB delay of 1. The MSB position of the
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
SLOT 4
SLOT 5
RIGHT 0
RIGHT 1
MSB
MSB
MSB
LSB
LSB
–2
–3
–4
+4
+3
MSB
MSB
MSB
LSB
–2
–3
–4
SLOT 6
BLANK SLOT
RIGHT 2
4 SCLK
LSB
LSB
LSB
+2
+1
polarity, a
BCLK
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