Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 534

Peripherals Routed Through the DAI
Table A-20. IDP_CTL1 Register Bit Descriptions
Bit Name
7–0 IDP_ENx
15–8 IDP_DMA_ENx
23–16 IDP_PINGx
24 Reserved
30–25 Reserved
31 IDP_FFCLR
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL)
The
IDP_PP_CTL
Table A-21) provides 20 mask bits that allow the input from any of the20
pins to be ignored.
For more information on the operation of the parallel data acquisition
port, see "Parallel Data Acquisition Port (PDAP)" on page
mation on the pin muxing that is used in conjunction with this module,
see "Pin Multiplexing" on page
A-50
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Description
IDP Channel x Enable. These are the enable bits for accept-
ing data from individual channels. Corresponding
IDP_ENx must be set with IDP_EN bit to get data from
Channel x. If IDP_EN bit is not set then this bit has no
effect. After
IDP DMA Enable. These are the DMA enable bits for indi-
vidual channels. Corresponding IPD_DMA_ENx must be
set with IDP_DMA_EN bit for DMA transfer of data from
Channel x. If DMA_EN bit is not set then this bit has no
effect. After
IDP ping-pong DMA Channel x Enable. These are the
Ping Pong DMA enable bits for individual channels. Corre-
sponding IDP_PINGx must be set to start Ping Pong DMA
from Channel x. This bit requires the IDP_DMA_ENx bit
and IDP_DMA_EN bit are set. After
are enabled.
Clear IDP FIFO. Setting this bit to 1 clears the IDP FIFO.
This is a write-only bit and always returns 0 on reads.
register (shown in Figure A-22
14-17.
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
all these bits are disabled.
RESET
all these bits are enabled.
RESET
and described in
all these bits
RESET
8-9. For infor-