Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 478

Processor Booting
32-Bit SPI Packing
Figure 14-12 shows how a 32-bit SPI host packs 48-bit instructions exe-
cuted at PM addresses 0x90000 and 0x90001. The 32-bit word is shifted
to internal program memory during the 256-word kernel load.
The following example shows a 48-bit instruction executed:
[0x90000] 0x112233445566
[0x90001] 0x7788AABBCCDD
MOSI/MISO
Figure 14-12. 32-Bit SPI Master/Slave Packing
The 32-bit SPI host packs or prearranges the data as:
SPI word 1= 0x33445566
SPI word 2 = 0xCCDD1122
SPI word 3 = 0x7788AABB
The initial boot of the 256-word loader kernel requires a 32-bit host to
transmit 384 x 32-bit words. The SPI DMA count value of 0x180 is equal
to 384 words.
14-44
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32 32
DMA
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
32
Internal
Memory
(IVT)