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Parallel Data Acquisition Port (PDAP)
high then clock edge is masked for data latching. It supports four types of
data packing mode selected by
Port Selection
The input to channel 0 of the IDP is multiplexed, and may be used either
in the serial mode or in a direct parallel input mode. Setting the
bit high disables the connection of SIP0 to channel 0 of the
IDP_PDAP_EN
FIFO. The data inputs can come either from the DAI pins or the external
port
pins. This is selected by the
ADDR
register.
IDP_PP_CTL
Figure 8-6
shows a block diagram of the PDAP.
IDP0_CLK_I
IDP0_FS_I
AD15:4
DAI_PB20:5
DAI_PB4:1
Figure 8-6. PDAP Block Diagram
8-10
www.BDTIC.com/ADI
MODE
PDAP_CLK_I
PDAP Control
PDAP_HOLD_I
INPUT DATA
DATA
LATCH
MASK
CHANNEL 0
UNIT
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
bits in the
IDP_PP_CTL
bit in the
IDP_PP_SELECT
PDAP_STRB_O
32-BIT
DATA
PACKING
UNIT
register.
DAI
UNIT
IDP_FIFO
SIP
DATA
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