Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 449

r0 = 4096;
lcntr = r0, do pllwait until lce;
pllwait: nop;
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP;
dm(PMCTL) = ustat2;
Listing 14-4. PLL Programming Example 2
ustat2 = dm(PMCTL);
bit set ustat2 PLLBP | PLLD4 |PLLM16;
/* set a multiplier of 16 and a divider of 4 and enable Bypass
mode*/
waiting_loop:
r0 = 4096;
lcntr = r0, do pllwait until lce;
pllwait: nop;
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP;
dm(PMCTL) = ustat2;
ustat2 = dm(PMCTL);
bit set ustat2 DIVEN;
/* Enable the DIVEN bit, PLL is now at
CLKIN*4 (CoreCLK = CLKIN * M/D = CLKIN* 16/4) */
dm(PMCTL) = ustat2
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
/* wait for PLL to lock at new rate
(requirement for VCO change) */
/* Reading the PMCTL register value
returns the DIVEN bit value as zero */
/* take PLL out of Bypass, PLL is now at
C LKIN*4 (CoreCLK = CLKIN * M/D = CLKIN * 16/4) */
/* The DIVEN bit should be cleared while
taking the PLL out of bypass mode */
/* wait for PLL to lock at new rate
(requirement for VCO change) */
/* take PLL out of Bypass*/
;
System Design
14-15